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Scaling of everything

Scaling of everything

Les besoins de demain reposent sur la nécessité de développer de nouveaux matériaux aux propriétés innovantes, essentiels pour innover dans tous les domaines et pour la compétitivité industrielle.

Published on 3 May 2024

Scaling of everything

Downscaling technologies are in great demand to develop ultra-low power solutions for future IoT and disruptive computing. Miniaturization is also required for smaller, lighter system packaging.

Computers have transformed society in the last 50 years thanks to the scaling of transistors and memory devices based on Moore’s law. This scaling law is now reaching its limits and system-on-chip integration is tending towards heterogeneity.

In heterogeneous systems, CMOS, memories and sensors are co-integrated on chips to yield ultra-low power solutions. Leti is currently developing an image recognition system that mimics neuronal networks [1, 2] Fig 1.

Future very small integrated systems will compute at very low energy using new paradigms and heterogeneous integration.

Our in-depth knowledge of FDSOI CMOS devices and silicon nanowire has openned up another research area at Leti around the development of Si quantum bits [3,4] Fig 2.

An increasing number of miniaturization technologies, advanced packaging and low weight are required for medical and transport applications, among others [5,6], Fig 3.


CMOS qubit device: a simplified 3D schematic of a dual-gate SOI nanowire field-effect transistor 


mplantable Low Profile Silicon box


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 Referenced publications in our annual research report 2015:

[1] Experimental Demonstration of Short and Long Term Synaptic Plasticity Using OxRAM Multi k-bit arrays for Reliable Detection in Highly Noisy Input Data T. Werner, E. o, O. Bichler, A. i, E. Nowak, J.-F. Nodin, B. Yvert, B. De Salvo, L.Perniola proceedings of IEDM 2016

[2] D. Garbin, E. Vianello et al. "HfO2-Based OxRAM Devices as Synapses for Convolutional Neural  Networks" Electron s, IEEE Transactions on 62 (8), 2494-2501 (2015)

[3] Si CMOS Platform for Quantum Information Processing L. Hutin,, R. Maurand,  D. Kotekar-Patil et al. Proceeding sof VLSI 2016

[4] A CMOS silicon spin qubit, R. Maurand, X. Jehl, D. Kotekar Patil et al.

[5] System-on-Wafer: 2-D and 3-D Technologies for Heterogeneous Systems, JC Souriau; N Sillon; J n; et al. IEEE Transactions on Components, Packaging and Manufacturing Technology  2011, Volume: 1, Issue: 6 p: 813 - 824,

[6] Implantable device including a MEMS r and an ASIC chip encapsulated in a hermetic silicon box for measurement of cardiac physiological parameter JC. Souriau; L. Castagné; G. t; G. Simon et al. 2014 IEEE 64th Electronic Components and Technolog
y Conference (ECTC)

ble device including a MEMter and an ASIC chip encapsulated in a hermetic silicon box for measurement of cardiac physl parameter